The present invention relates to circuitry for reading from and writing to memory cells.
As general purpose and embedded microprocessors increase in clock frequency and performance, on-chip memories are provided to reduce the pin bandwidth (that is the number of pins) required by these microprocessors. By having the integrated circuit memory on chip, input and output pins to access an external memory are redundant or alternatively the number of accesses to an external location can be reduced, allowing pins to be used for a plurality of different functions. For high performance processors, these on-chip memories can consume a significant portion of the total chip area. This can have the disadvantage that the total chip area can be increased. This is undesirable.
On-chip memories typically handle four fundamental operations:
(1) load from a location (on chip). This involves single words being loaded in a clock cycle.
(2) store to a location (on chip). This involves single words being stored in a cycle.
(3) write a block of data into the on-chip memory for example from an external memory. This may involve a number of words, for example 4, 8 or 16.
(4) read a block of data from the on-chip memory often sending the data to an external memory. This may involve a number of words, for example 4, 8 or 16.
The first two operations take place on chip, wherein the second two operations involve off-chip locations.
Blocks of data are written into the on-chip memory from an external memory source. A microprocessor on the chip may utilise this data and perhaps other data to perform a calculation and the results of this calculation may be used to update the data stored in the on chip memory. If a new block of data needs to be loaded into the on-chip memory the block being replaced might be one which had been changed since it has been loaded. Hence before the new data is loaded, the current block of data may need to be read and stored in another location. This location would typically be an external memory.
Generally memory cells which form an on-chip memory array are divided into groups of smaller numbers (for example 4) of memory cells with each group having read and write circuitry to allow data to be read from and written to the cells in the array. This grouping of cells is used because the sensing circuitry used to read data from cells is physically large relative to a single memory cell. Therefore the memory cells share sensing circuitry to avoid having to enlarge the memory array unnecessarily to accommodate sensing circuitry for each cell. In the past data has been written to and read from such memory groups at the same rate. That is to say only one cell in each group may be written to or read from in any one cycle.
However, it is sometimes required that a block of data be written to a relatively large number of memory cells in the on-chip memory. Since each cell in each group can only be written to at any one time a group having four cells will require four write cycles to write data into the group of cells. This type of operation is sometimes referred to as a block write operation. This relatively large number of clock cycles can delay the operation of the chip.
It is desirable that load store operations to and from on-chip memory occur more frequently than reading/writing operations where blocks of data are read from and written to the on-chip memory. Typically a system will be optimized such that the simple load/store operations require fewer cycles that is one cycle than do block read/write operations. Furthermore, since data stored in the on-chip memory often ends up being read only data, the write operation may occur more frequently than the read operation. Although block read/write operations may be less frequent than simple load/store operations, with large sparse (that is data which only use one or two words out of four or eight words) data sets, the time spent performing block operations can often be significant as discussed previously. Since the processor is halted while the block write operation is in progress, the time taken by this operation can have a significant impact in overall system performance. This is clearly disadvantageous.
One method of increasing the write data width of a RAM block would be to make a new RAM block by grouping together smaller numbers of cells. In other words, the number of cells in each group is reduced. Hence to double the write data width, the original RAM block is cut in half in such a manner that the original read/write data width ratios are retained. By grouping two of these blocks together one can generate a block which has twice the read and twice the write data width as the original blocks. However this approach would end up increasing the resulting effective RAM block size silicon area by approximately 10% and would require additional wiring resources to wire the smaller RAM blocks together to form the larger block. This is disadvantageous.
It is an object of embodiments of the present invention to address or at least mitigate these problems.
According to the present invention there is provided circuitry for reading from and writing to memory cells of a group of memory cells, said circuitry comprising read circuitry and write circuitry each connectable to respective bit lines associated with respective ones of said memory cells, wherein said read circuitry being arranged to read from said cells and said write circuitry being arranged to write to said cells, said read circuitry and write circuitry are configured so that more cells in said group can be simultaneously written to during a write operation than can be simultaneously read from during a read operation.
Embodiments of the present invention permit the time taken to write a block of data to be reduced without significantly increasing the area of an on-chip memory. Embodiments of the invention may use an efficient on-chip RAM architecture which may permit the required area for the memory to be relatively small.